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An Approach to Manage Reconfigurations and Reduce Area Cost in Hard Real-Time Reconfigurable Systems
This article presents a methodology to build real-time reconfigurable systems that ensure that all the temporal constraints of a set of applications are met, while optimizing the utilization of the available reconfigurable resources. Starting fr[...]texto impreso
Olivito, Javier ; Serrano, Felipe ; Clemente Barreira, Juan Antonio ; Mecha, Hortensia ; Resano, Javier | Institution of Engineering and Technology | 2018-01-16In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad [...]texto impreso
Ramezani, Reza ; Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier | Elsevier | 2020-05-20This paper addresses the problem of hardware tasks reliability estimation in harsh environments. A novel statistical model is presented to estimate the reliability, the mean time to failure, and the number of errors of hardware tasks running on [...]texto impreso
Clemente Barreira, Juan Antonio ; Pérez Ramo, Elena ; Resano, Javier ; Mozos Muñoz, Daniel ; Catthoor, Francky | IEEE | 2014-06In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can introduce important overheads, both in terms of energy consumption and time, especially when configurations are fetched from an external memory. In or[...]texto impreso
Fabero Jiménez, Juan Carlos ; Mendías Cuadros, José Manuel ; Mecha López, Hortensia ; González Calvo, Carlos ; Clemente Barreira, Juan Antonio | 2015-02-11Se plantea la adaptación y ampliación de la placa de periféricos desarrollada el curso anterior para su uso en otras asignaturas impartidas en nuestra Facultad, como son "Sistemas Empotrados Distribuidos" y "Programación de Sistemas y Dispositiv[...]texto impreso
Ramos, Pablo ; Vargas Vallejo, Vanessa Carolina ; Baylac, Maud ; Villa, Francesca ; Rey, Solenne ; Clemente Barreira, Juan Antonio ; Zergainoh, Nacer-Eddine ; Méhaut, Jean-François | IEEE | 2016-08The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric M[...]texto impreso
Ramos, Pablo ; Vargas, Vanessa ; Baylac, Maud ; Villa, Francesca ; Rey, Solenne ; Clemente Barreira, Juan Antonio ; Zergainoh, Nacer-Eddine ; Méhaut, Jean-François ; Velazco, Raoul | IEEE Nuclear and Plasma Sciences Society | 2016-07-12The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric M[...]texto impreso
Rezaei, Mohammadreza ; Martín Holgado, Pedro ; Morilla, Yolanda ; Franco Peláez, Francisco Javier ; Fabero Jiménez, Juan Carlos ; Mecha López, Hortensia ; Puchner, Helmut ; Hubert, Guillaume ; Clemente Barreira, Juan Antonio | IEEE-Inst Electrical Electronics Engineers Inc | 2020-10This article presents an experimental study on the sensitivity of a commercial-off-the-shelf (COTS) bulk 65-nm static random access memory (SRAM) under 15.6 MeV proton irradiation when powered up at ultralow bias voltage. Tests were run on stand[...]texto impreso
Velazco, Raoul ; Clemente Barreira, Juan Antonio ; Hubert, Guillaume ; Mansour, Wassim ; Palomar Trives, Carlos ; Franco Peláez, Francisco Javier ; Baylac, Maud ; Rey, Solenne ; Rosetto, Olivier ; Villa, Francesca | IEEE-Inst Electrical Electronics Engineers Inc | 2014-12Radiation tests with 15-MeV neutrons were performed in a COTS SRAM including a new memory cell design combining SRAM cells and DRAM capacitors to determine if, as claimed, it is soft-error free and to estimate upper bounds for the cross-section.[...]texto impreso
Korkian, Golnaz ; Rahmanikia, Navid ; Noori, Hamid ; Clemente Barreira, Juan Antonio | 2017-03-18During the last decades, technology scaling in reconfigurable logic devices enabled implementing complicated designs which results in higher power density and on-chip temperature. Since higher operating temperature of chips is a critical problem[...]texto impreso
Clemente Barreira, Juan Antonio ; Gran, Rubén ; Chocano Gómez, Abel ; Prado, Carlos del ; Resano, Javier | IEEE | 2015-04-16The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip configuration memory is included in the system because it can reduce both the reconfiguration latency and its energy consumption. However, FPGA o[...]texto impreso
Clemente Barreira, Juan Antonio ; Mansour, Wassim ; Ayoubi, Rafic ; Serrano, Felipe ; Mecha López, Hortensia ; Ziade, Haissam ; El Falou, Wassim ; Velazco, Raoul | Elsevier | 2016-01-01This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault toleran[...]texto impreso
Clemente Barreira, Juan Antonio ; Resano, Javier ; González Calvo, Carlos ; Mozos Muñoz, Daniel | IEEE | 2011-07New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader u[...]texto impreso
Clemente Barreira, Juan Antonio ; González, Carlos ; Resano, Javier ; Mozos Muñoz, Daniel | 2008-12-30Reconfigurable hardware can be used to build a multitasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs an[...]texto impreso
Resano, Javier ; Clemente Barreira, Juan Antonio ; González, Carlos ; García, José Luis ; Mozos Muñoz, Daniel | 2007Reconfigurable HW can be used to build a hardware multitasking system where tasks can be assigned to the reconfigurable HW at run-time according to the requirements of the running applications. Normally the execution in this kind of systems is c[...]
