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Autor Clemente Barreira, Juan Antonio |
Documentos disponibles escritos por este autor (39)
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An Approach to Manage Reconfigurations and Reduce Area Cost in Hard Real-Time Reconfigurable Systems
This article presents a methodology to build real-time reconfigurable systems that ensure that all the temporal constraints of a set of applications are met, while optimizing the utilization of the available reconfigurable resources. Starting fr[...]![]()
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Olivito, Javier ; Serrano, Felipe ; Clemente Barreira, Juan Antonio ; Mecha, Hortensia ; Resano, Javier | Institution of Engineering and Technology | 2018-01-16In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad [...]![]()
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Ramezani, Reza ; Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier | Elsevier | 2020-05-20This paper addresses the problem of hardware tasks reliability estimation in harsh environments. A novel statistical model is presented to estimate the reliability, the mean time to failure, and the number of errors of hardware tasks running on [...]![]()
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Clemente Barreira, Juan Antonio ; Pérez Ramo, Elena ; Resano, Javier ; Mozos Muñoz, Daniel ; Catthoor, Francky | IEEE | 2014-06In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can introduce important overheads, both in terms of energy consumption and time, especially when configurations are fetched from an external memory. In or[...]![]()
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Fabero Jiménez, Juan Carlos ; Mendías Cuadros, José Manuel ; Mecha López, Hortensia ; González Calvo, Carlos ; Clemente Barreira, Juan Antonio | 2015-02-11Se plantea la adaptación y ampliación de la placa de periféricos desarrollada el curso anterior para su uso en otras asignaturas impartidas en nuestra Facultad, como son "Sistemas Empotrados Distribuidos" y "Programación de Sistemas y Dispositiv[...]![]()
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Ramos, Pablo ; Vargas Vallejo, Vanessa Carolina ; Baylac, Maud ; Villa, Francesca ; Rey, Solenne ; Clemente Barreira, Juan Antonio ; Zergainoh, Nacer-Eddine ; Méhaut, Jean-François | IEEE | 2016-08The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric M[...]![]()
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Ramos, Pablo ; Vargas, Vanessa ; Baylac, Maud ; Villa, Francesca ; Rey, Solenne ; Clemente Barreira, Juan Antonio ; Zergainoh, Nacer-Eddine ; Méhaut, Jean-François ; Velazco, Raoul | IEEE Nuclear and Plasma Sciences Society | 2016-07-12The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric M[...]![]()
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Rezaei, Mohammadreza ; Martín Holgado, Pedro ; Morilla, Yolanda ; Franco Peláez, Francisco Javier ; Fabero Jiménez, Juan Carlos ; Mecha López, Hortensia ; Puchner, Helmut ; Hubert, Guillaume ; Clemente Barreira, Juan Antonio | IEEE-Inst Electrical Electronics Engineers Inc | 2020-10This article presents an experimental study on the sensitivity of a commercial-off-the-shelf (COTS) bulk 65-nm static random access memory (SRAM) under 15.6 MeV proton irradiation when powered up at ultralow bias voltage. Tests were run on stand[...]![]()
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Velazco, Raoul ; Clemente Barreira, Juan Antonio ; Hubert, Guillaume ; Mansour, Wassim ; Palomar Trives, Carlos ; Franco Peláez, Francisco Javier ; Baylac, Maud ; Rey, Solenne ; Rosetto, Olivier ; Villa, Francesca | IEEE-Inst Electrical Electronics Engineers Inc | 2014-12Radiation tests with 15-MeV neutrons were performed in a COTS SRAM including a new memory cell design combining SRAM cells and DRAM capacitors to determine if, as claimed, it is soft-error free and to estimate upper bounds for the cross-section.[...]![]()
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Korkian, Golnaz ; Rahmanikia, Navid ; Noori, Hamid ; Clemente Barreira, Juan Antonio | 2017-03-18During the last decades, technology scaling in reconfigurable logic devices enabled implementing complicated designs which results in higher power density and on-chip temperature. Since higher operating temperature of chips is a critical problem[...]![]()
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Clemente Barreira, Juan Antonio ; Gran, Rubén ; Chocano Gómez, Abel ; Prado, Carlos del ; Resano, Javier | IEEE | 2015-04-16The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip configuration memory is included in the system because it can reduce both the reconfiguration latency and its energy consumption. However, FPGA o[...]![]()
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Clemente Barreira, Juan Antonio ; Mansour, Wassim ; Ayoubi, Rafic ; Serrano, Felipe ; Mecha López, Hortensia ; Ziade, Haissam ; El Falou, Wassim ; Velazco, Raoul | Elsevier | 2016-01-01This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault toleran[...]![]()
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Clemente Barreira, Juan Antonio ; Resano, Javier ; González Calvo, Carlos ; Mozos Muñoz, Daniel | IEEE | 2011-07New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader u[...]![]()
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Clemente Barreira, Juan Antonio ; González, Carlos ; Resano, Javier ; Mozos Muñoz, Daniel | 2008-12-30Reconfigurable hardware can be used to build a multitasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs an[...]![]()
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Resano, Javier ; Clemente Barreira, Juan Antonio ; González, Carlos ; García, José Luis ; Mozos Muñoz, Daniel | 2007Reconfigurable HW can be used to build a hardware multitasking system where tasks can be assigned to the reconfigurable HW at run-time according to the requirements of the running applications. Normally the execution in this kind of systems is c[...]![]()
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Hubert, Guillaume ; Aubry, Sébastien ; Clemente Barreira, Juan Antonio | The Institute of Electrical and Electronics Engineers (IEEE) | 2020-03-02This article proposes to study the impact of ground-level enhancement (GLE) induced by extreme solar flares on the soft error rate (SER) for flight representatives to the world-air traffic. A GLE physical model was confronted to cosmic ray varia[...]![]()
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El HW reconfigurable se puede utilizar para construir un sistema multitarea en el que las tareas puedan asignarse en tiempo de ejecución a los recursos reconfigurables según las necesidades de las aplicaciones. En estos sistemas, las tareas se r[...]![]()
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Franco Peláez, Francisco Javier ; Clemente Barreira, Juan Antonio ; Mecha López, Hortensia ; Velazco, Raoul | IEEE | 2019-03-01After having carried out radiation experiments on memories, the detected bitflips must be classified into single bit upsets and multiple events to calculate the cross sections of different phenomena. There are some accepted procedures to determi[...]![]()
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Franco Peláez, Francisco Javier ; Clemente Barreira, Juan Antonio ; Korkian, Golnaz ; Fabero Jiménez, Juan Carlos ; Mecha López, Hortensia ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2020In radiation tests on SRAMs or FPGAs, two or more independent bitflips can be misled with a multiple event if they accidentally occur in neighbor cells. In the past, different tests such as the ``birthday statistics'' have been proposed to estim[...]![]()
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Este documento es una traducción al inglés del tutorial escrito por Marcos Sánchez-Élez Martín, titulado "Introducción a la programación en VHDL", depositado en E-Prints bajo la URL http://eprints.ucm.es/26200/.![]()
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Clemente Barreira, Juan Antonio ; Beretta, Ivan ; Rana, Vincenzo ; Atienza, David ; Sciuto, Donatella | ACM | 2014-06-01Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applic[...]![]()
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This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the F[...]![]()
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Sáez Alcaide, Juan Carlos ; Sánchez-Elez Martín, Marcos ; Risco Martín, José Luis ; Castro Rodríguez, Fernando ; Prieto Matías, Manuel ; Sáez Puche, Regino ; Chaver Martínez, Daniel ; Olcoz Herrero, Katzalin ; Clemente Barreira, Juan Antonio ; Igual Peña, Francisco ; García García, Adrián ; Sánchez Foces, David | 2018-06-30La internacionalización de la docencia ofrece grandes oportunidades para la Universidad, pero también plantea retos significativos para estudiantes y profesores. En particular, la creación y mantenimiento efectivo del material docente de una as[...]![]()
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Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier ; Vila, Francesca ; Baylac, Maud ; Ramos Vargas, Pablo Francisco ; Vargas Vallejo, Vanessa Carolina ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2015-09-18This paper presents an experimental study of the sensitivity to 15-MeV neutrons at low bias voltage of advanced low-power SRAMs by Renesas Electronics. The most interesting results are the occurrence of clusters of bitflips, hard errors only vis[...]![]()
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La computación reconfigurable es una tecnología prometedora que permite ejecutar con gran eficiencia aplicaciones con una alta carga computacional y/o un comportamiento dinámico difícil o imposible de predecir, a la vez que reutilizar los mismos[...]![]()
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Botella Juan, Guillermo ; Barrio García, Alberto Antonio Del ; García Sanchez, Carlos ; Clemente Barreira, Juan Antonio ; Bernabé García, Sergio ; Roa Romero, Carlos ; Ahmed Fahmy Amin, Hesham ; Ezquerro Rodríguez, José Miguel ; Cao García, Francisco Javier ; Sierra López, Angel | 2019-08-01Los objetivos alcanzados en el proyecto han sido: I) Continuar la preparación del framework de desarrollo rápido de código VHDL sobre FPGAs de Altera a partir de código Matlab y del entorno gráfico Simulink realizado en el proyecto ALLIANCE (PID[...]![]()
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Ramezani, Reza ; Sedaghat, Yasser ; Clemente Barreira, Juan Antonio | The Institute of Electrical and Electronics Engineers (IEEE) | 2017-04This study presents a technique to improve the reliability and the Mean Time to Failure (MTTF) of hardware task graphs running on reconfigurable computers. This tech- nique, which has been named Task Early-fetch, can be applied to a sequence of [...]![]()
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Clemente Barreira, Juan Antonio ; Mozos Muñoz, Daniel ; Resano, Javier | 2011-09-01Dynamically reconfigurable hardware is a promising technology that combines in the same device both the high performance and the flexibility that many recent applications demand. However, one of its main drawbacks is the reconfiguration overhead[...]![]()
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Clemente Barreira, Juan Antonio ; Hubert, Guillaume ; Franco Peláez, Francisco Javier ; Vila, Francesca ; Baylac, Maud ; Puchner, Helmut ; Velazco, Raoul ; Mecha López, Hortensia | IEEE-Inst Electrical Electronics Engineers Inc | 2017-08-01This paper presents the characterization of the sensitivity to 14-MeV neutrons of a Commercial Off-The-Shelf (COTS) 90-nm Static Random Access Memories (SRAMs) manufactured by Cypress Semiconductor, when biased at ultra low voltage. Firstly, exp[...]![]()
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Clemente Barreira, Juan Antonio ; Hubert, Guilaume ; Fraire, Juan ; Franco Peláez, Francisco Javier ; Villa, Francesca ; Rey, Solenne ; Baylac, Maud ; Puchner, Helmut ; Mecha, Hortensia ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2018-02-01This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed f[...]![]()
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Fabero Jiménez, Juan Carlos ; Mecha López, Hortensia ; Franco Peláez, Francisco Javier ; Clemente Barreira, Juan Antonio ; Korkian, Golnaz ; Rey, Solenne ; Cheymol, Benjamin ; Baylac, Maud ; Hubert, Guillaume ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2020A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and [...]![]()
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Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier ; Villa, Francesca ; Baylac, Maud ; Ramos Vargas, Pablo Francisco ; Vargas Vallejo, Vanessa Carolina ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2016-08-16This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characteri[...]![]()
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Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier ; Villa, Francesca ; Rey, Sole ; Baylac, Maud ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Puchner, Helmut ; Hubert, Guillaume ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2015-09-18This paper presents an approach to discern MCUs from SEUs in SRAM memories. Experiments involving radiation tests with 14-MeV neutrons on two successive generations (130 and 90 nm) of Cypress devices are presented.![]()
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Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier ; Villa, Francesca ; Baylac, Maud ; Rey, Solenne ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Puchner, Helmut ; Hubert, Guillaume ; Velazco, Raoul | IEEE | 2016-08Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Fie[...]![]()
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Franco Peláez, Francisco Javier ; Clemente Barreira, Juan Antonio ; Baylac, Maud ; Rey, Solenne ; Villa, Francesca ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Puchner, Helmut ; Hubert, Guillaume ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2017-08-01This paper addresses a well-known problem that occurs when memories are exposed to radiation: the determination if a bitflip is isolated or if it belongs to a multiple event. As it is unusual to know the physical layout of the memory, this paper[...]![]()
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Serrano, Felipe ; Clemente Barreira, Juan Antonio ; Mecha López, Hortensia | 2014-10-30In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device[...]![]()
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Clemente Barreira, Juan Antonio ; González Calvo, Carlos ; Resano, Javier ; Mozos Muñoz, Daniel | Elsevier | 2010-03Reconfigurable hardware can be used to build multi tasking systems that dynamically adapt themselves to the requirements of the running applications. This is especially useful in embedded systems, since the available resources are very limited a[...]![]()
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Clemente Barreira, Juan Antonio | Universidad Complutense de Madrid, Servicio de Publicaciones | 2011-05-16El principal objetivo de esta tesis es reducir, el impacto de las reconfiguraciones generadas por la ejecución de tareas en sistemas reconfigurables utilizados en entornos altamente dinámicos. Para ello, este trabajo propone un algoritmo de plan[...]![]()
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Botella Juan, Guillermo ; Del Barrio García, Alberto ; Clemente Barreira, Juan Antonio ; López Alonso, José Manuel ; Ezquerro Rodríguez, José Miguel ; Piquer Otero, Andrés ; Carrascal de la Heras, Ginés ; Roa Romero, Carlos ; Mas Aguilar, Juan ; Fahmy Amin, Hesham Ahmed ; García Moreno, Daniel ; Aguilera Calle, Iván ; Sierra López, Angel ; Cao García, Francisco Javier | 2020-07-21Desarrollar un intérprete de signos en tiempo real mediante técnicas de aprendizaje profundo, aceleradores y procesado de video inteligente con objeto de desarrollar tiflotecnología barata, portable y accesible para toda la universidad.