Información del autor
Documentos disponibles escritos por este autor (4)
Añadir el resultado a su cesta Hacer una sugerencia Refinar búsqueda
texto impreso
Olivito, Javier ; Serrano, Felipe ; Clemente Barreira, Juan Antonio ; Mecha, Hortensia ; Resano, Javier | Institution of Engineering and Technology | 2018-01-16In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad [...]texto impreso
Clemente Barreira, Juan Antonio ; Mansour, Wassim ; Ayoubi, Rafic ; Serrano, Felipe ; Mecha López, Hortensia ; Ziade, Haissam ; El Falou, Wassim ; Velazco, Raoul | Elsevier | 2016-01-01This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault toleran[...]texto impreso
This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the F[...]texto impreso
Serrano, Felipe ; Clemente Barreira, Juan Antonio ; Mecha López, Hortensia | 2014-10-30In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device[...]
