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Título:
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LFSR-based bit-serial GF(^2m) multipliers using irreducible trinomials
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Autores:
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Imaña Pascual, José Luis
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Tipo de documento:
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texto impreso
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Editorial:
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Institute of Electrical and Electronics Engineers (IEEE), 2021-01-01
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Dimensiones:
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application/pdf
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Nota general:
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info:eu-repo/semantics/openAccess
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Idiomas:
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Palabras clave:
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Estado = Publicado
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Materia = Ciencias: Informática: Inteligencia artificial
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Tipo = Artículo
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Resumen:
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In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the binary extension field GF(^2m) generated by irreducible trinomials is presented. Bit-serial GF(^2m) PB multiplication offers a performance/area trade-off that is very useful in resource constrained applications. The architecture here proposed is based on LFSR (Linear-Feedback Shift Register) and can perform a multiplication in m clock cycles with a constant propagation delay of T_A + T_X. These values match the best time results found in the literature for bit-serial PB multipliers with a slight reduction of the space complexity. Furthermore, the proposed architecture can perform the multiplication of two operands for t different finite fields GF(^2m) generated by t irreducible trinomials simultaneously in m clock cycles with the inclusion of t(m - 1) flipflops and tm XOR gates.
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En línea:
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https://eprints.ucm.es/id/eprint/63571/1/Iman%CC%83a22postprint.pdf
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