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Título:
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Reconfigurable implementation of GF(2^m) bit-parallel multipliers
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Autores:
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Imaña Pascual, José Luis
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Tipo de documento:
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texto impreso
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Editorial:
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IEEE, 2018-04-23
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Dimensiones:
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application/pdf
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Nota general:
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info:eu-repo/semantics/openAccess
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Idiomas:
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Palabras clave:
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Estado = Publicado
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Materia = Ciencias: Informática: Inteligencia artificial
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Tipo = Sección de libro
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Resumen:
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Hardware implementations of arithmetic operations over binary finite fields GF(2^m) are widely used in several important applications, such as cryptography, digital signal processing and error-control codes. In this paper, efficient. reconfigurable implementations of bit-parallel canonical basis multipliers over binary fields generated by type II irreducible pentanomials f_(y) = y^m + y^(n+2) + y^(n+1) + y^n + 1 are presented. These pentanomials are important because all five binary fields recommended by NIST for ECDSA can be constructed using such polynomials. In this work, a new approach for CF(2^m) multiplication based on type II pentanomials is given and several post-place and route implementation results in Xilinx Artix-7 FPGA are reported. Experimental results show that the proposed multiplier implementations improve the area x time parameter when compared with similar multipliers found in the literature.
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En línea:
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https://eprints.ucm.es/55397/1/ima%C3%B1a18postprint.pdf
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