|
Título:
|
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA
|
|
Autores:
|
Olivito, Javier ;
Serrano, Felipe ;
Clemente Barreira, Juan Antonio ;
Mecha, Hortensia ;
Resano, Javier
|
|
Tipo de documento:
|
texto impreso
|
|
Editorial:
|
Institution of Engineering and Technology, 2018-01-16
|
|
Dimensiones:
|
application/pdf
|
|
Nota general:
|
info:eu-repo/semantics/openAccess
|
|
Idiomas:
|
|
|
Palabras clave:
|
Estado = En prensa
,
Materia = Ciencias: Informática: Circuitos integrados
,
Materia = Ciencias: Informática: Hardware
,
Materia = Ciencias: Informática: Electrónica
,
Tipo = Artículo
|
|
Resumen:
|
In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.
|
|
En línea:
|
https://eprints.ucm.es/id/eprint/46629/1/IET-CDT.2016.0095.pdf
|
