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Ramos, Pablo ; Vargas Vallejo, Vanessa Carolina ; Baylac, Maud ; Villa, Francesca ; Rey, Solenne ; Clemente Barreira, Juan Antonio ; Zergainoh, Nacer-Eddine ; Méhaut, Jean-François | IEEE | 2016-08The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric M[...]texto impreso
Ramos, Pablo ; Vargas, Vanessa ; Baylac, Maud ; Villa, Francesca ; Rey, Solenne ; Clemente Barreira, Juan Antonio ; Zergainoh, Nacer-Eddine ; Méhaut, Jean-François ; Velazco, Raoul | IEEE Nuclear and Plasma Sciences Society | 2016-07-12The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric M[...]texto impreso
Velazco, Raoul ; Clemente Barreira, Juan Antonio ; Hubert, Guillaume ; Mansour, Wassim ; Palomar Trives, Carlos ; Franco Peláez, Francisco Javier ; Baylac, Maud ; Rey, Solenne ; Rosetto, Olivier ; Villa, Francesca | IEEE-Inst Electrical Electronics Engineers Inc | 2014-12Radiation tests with 15-MeV neutrons were performed in a COTS SRAM including a new memory cell design combining SRAM cells and DRAM capacitors to determine if, as claimed, it is soft-error free and to estimate upper bounds for the cross-section.[...]texto impreso
Clemente Barreira, Juan Antonio ; Hubert, Guilaume ; Fraire, Juan ; Franco Peláez, Francisco Javier ; Villa, Francesca ; Rey, Solenne ; Baylac, Maud ; Puchner, Helmut ; Mecha, Hortensia ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2018-02-01This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed f[...]texto impreso
Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier ; Villa, Francesca ; Baylac, Maud ; Ramos Vargas, Pablo Francisco ; Vargas Vallejo, Vanessa Carolina ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2016-08-16This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characteri[...]texto impreso
Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier ; Villa, Francesca ; Rey, Sole ; Baylac, Maud ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Puchner, Helmut ; Hubert, Guillaume ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2015-09-18This paper presents an approach to discern MCUs from SEUs in SRAM memories. Experiments involving radiation tests with 14-MeV neutrons on two successive generations (130 and 90 nm) of Cypress devices are presented.texto impreso
Clemente Barreira, Juan Antonio ; Franco Peláez, Francisco Javier ; Villa, Francesca ; Baylac, Maud ; Rey, Solenne ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Puchner, Helmut ; Hubert, Guillaume ; Velazco, Raoul | IEEE | 2016-08Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Fie[...]texto impreso
Franco Peláez, Francisco Javier ; Clemente Barreira, Juan Antonio ; Baylac, Maud ; Rey, Solenne ; Villa, Francesca ; Mecha López, Hortensia ; Agapito Serrano, Juan Andrés ; Puchner, Helmut ; Hubert, Guillaume ; Velazco, Raoul | IEEE-Inst Electrical Electronics Engineers Inc | 2017-08-01This paper addresses a well-known problem that occurs when memories are exposed to radiation: the determination if a bitflip is isolated or if it belongs to a multiple event. As it is unusual to know the physical layout of the memory, this paper[...]
